1. Technical Field
The present invention relates in general to electrical circuits and more particularly, to a modulator reference circuit having a variable voltage generator.
2. Description of the Related Art
Many signal processing systems, such as audio processing systems, utilize delta-sigma modulators (also referred to as sigma-delta modulators) to provide output data with high, in-band signal to noise ratio. Analog-to-digital conversion delta-sigma modulators conventionally include, among other components, one or more integrators built with operational amplifiers (op-amps), capacitors, switches and voltage references. As is well-known to those skilled in the art, op-amp integrators typically employ a constant DC voltage reference, which is sampled and fed into at least the first integrator.
FIG. 1A depicts a conventional single-ended integrator circuit 100 for a delta-sigma modulator. As shown, integrator circuit 100 includes a voltage generator 102 that generates constant positive and negative reference voltages Vref+ and Vref−, which are typically of equal magnitude. Integrator circuit 100 further includes a reference capacitor (Cref) 104, and an op-amp 106 having a grounded positive input and a capacitor (Cint) 108 in its negative feedback loop. The top plate of Cref 104 is selectively coupled to the negative input of op-amp 106 by a first switch 110 that is closed when timing signal φ1 is asserted, and is further selectively coupled to reference node 120 by a second switch 112 that is closed when timing signal φ2 is asserted. A third switch 116, which is controlled by Vref_ctrl signal 118, selects the polarity of the reference voltage applied to reference node 120.
The input signal provided to the delta-sigma modulator by source 114, which is coupled to the negative input of op-amp 106, can either be a current or a voltage. Often when the input signal is a voltage, the voltage is periodically sampled through an input sampling network similar to the reference sampling network comprising switches 110, 112 and capacitor 104.
FIG. 1B is a timing diagram depicting the DC reference voltage supplied by voltage generator 102 through switch 116 to reference node 120 in relation to timing signals φ1 and φ2 and Vref_ctrl signal 118. In operation, when timing signal φ1 is deasserted and timing signal φ2 is asserted, first switch 110 opens and second switch 112 closes, causing the reference voltage selected by Vref_ctrl signal 118 for application to reference node 120 (i.e., either Vref+ or Vref−) to be sampled onto Cref 104. Subsequently, when timing signal φ1 is asserted and timing signal φ2 is deasserted, the charge Q stored by Cref 104, which is given by Q=Cref×Vref, is transferred from Cref 104 to Cint 108. At the end of the assertion of timing signal φ1, Cref 104 is almost if not completely discharged, and the voltage on its top plate is approximately 0V. Consequently, when second switch 112 closes in response to assertion of φ2, second switch 112 has a positive or negative voltage across its terminals equal in magnitude to Vref.